Synthesis of systems specified as interacting VHDL processes

This paper presents an approach to synthesis of hardware systems specified as interacting VHDL processes. Different from traditional high-level synthesis methodologies our approach takes into account the interactions and interdependence between concurrent processes. Two methods have been developed. The first method supports an unrestricted use of signals and wait statements and synthesizes synchronous hardware with global control of process synchronization for signal update. The second method allows hardware synthesis without the strict synchronization required by the VHDL simulation-based semantics. In both methods VHDL system specifications are first translated into an internal design representation based on timed Petri nets, which is then synthesized into hardware implementation structures at register-transfer level. Our main objective is to preserve simulation/ synthesis correspondence during synthesis and to produce hardware that operates with a high degree of parallelism. Experimental results with practical design examples demonstrate that the proposed methods are efficient in terms of both resulted hardware and optimization time.